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Evolutionary Computation applied to Analog IC Design Automation

Nuno Horta, PhD
Professor Department of Electrical and Computer Engineering
Instituto Superior Técnico, Technical University of Lisbon
Instituto de Telecomunicações
Lisbon, Portugal


In the last decades, Very Large Scale Integration (VLSI) technologies have been widely improved, allowing the proliferation of consumer electronics and enabling the growth of integrated circuits (IC) market from $10 billion in 1980 to over than $300 billion in 2013, according to IC Insights Inc. IC designers are building systems that are increasingly more complex and integrated. The need of new functionalities, smaller devices, longer battery life, more power efficiency, less production and integration costs, and less design cost makes the design of electronic systems a truly challenging task. The complexity of electronic systems design and the strict time-to-market impose the use of Computer Aided Design (CAD) tools to support the design process.

In digital IC design, mature Electronic Design Automation (EDA) tools and design methodologies are available helping the designers to keep up with the new capabilities offered by the technology. Currently almost all low-level phases of the process are automated. The level of automation is far from the push-button stage, but is keeping up reasonably well with the complexity supported by the technology. On the other hand, analog IC design automation tools strive to keep up with the new challenges created by deep nanometer technologies. Due to the lack of automation, designers still explore the solution space almost manually. This method causes long design times, and allied to the non-reusable nature of analog IC, makes analog IC design a cumbersome task. The use of evolutionary computation (EC) techniques in analog IC design automation is wide spreading from system level to physical level design. Particularly, the exploration of new topologies and the optimal sizing at system and circuit level using evolutionary multi-objective optimization (EMO) approaches, as well as, the placement and routing optimization at physical level using EC techniques are application examples in the area of analog IC design automation. The benefits of EC are huge in terms of design time reduction and also in terms of improved integrated circuits performance.

This tutorial addresses the application of EC to analog IC design automation. First, a brief introduction to the analog IC design flow, from system and circuit level performance and functional specifications to the integrated circuit layout, will be presented. Then, the existing analog IC design automation solutions will be reviewed. Next, the main part of this tutorial, the application of EMO techniques to circuit sizing optimization, as well as, the application of EC techniques to automatic layout generation will be discussed including the presentation of some practical examples. Finally, the future trends on EC applied to analog IC design will be highlighted.

Expected Enrollment: Researchers, engineers and students interested in real world applications of EC and EMO.



Nuno Horta (IEEE S’89–M’97–SM’11) received the Licenciado, M.Sc. and Ph.D. degrees in electrical engineering from Instituto Superior Técnico (IST), Technical University of Lisbon, Portugal, in 1989, 1992 and 1997, respectively. In March 1998, he joined the IST Electrical and Computer Engineering Department. Since 1998, he is, also, with Instituto de Telecomunicações, where he is presently the head of the Integrated Circuits Group. He has authored or co-authored more than 100 publications as books, book chapters, international journals papers and conferences papers. He has also participated as researcher or coordinator in several National and European R&D projects. His research interests are mainly in analog and mixed-signal IC design, analog IC design automation and soft computing.


The length of the tutorial:
two hours.


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